1. Field of the Invention
This invention relates to EPROM, flash memory cells and more particularly to high coupling ratio devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,089,867 describes increasing the coupling ratio by texturizing the polysilicon 1 surface.
FIG. 1 is a plan view of a prior art device 10 with several polysilicon 1 floating gate lines FG1, FG2, FG3, and FG4 parallel polysilicon 2 word lines 20 and 20' forming control gates. The floating gate lines FG1 and FG2 are located beneath polysilicon 2 word line 20 and are separated by distance "d". The minimum value of "d" is limited by the design rule. The polysilicon 1/polysilicon 1 spacing "d" is minimum based on the design rule. For example, "d" is about 0.6 .mu.m for a 0.6 .mu.m process for producing a product with that scale. The floating gate lines FG3 and FG4 are located beneath polysilicon 2 word line 20'. A number of contacts X1, X2, X3, and X4 are shown adjacent to the floating gate lines FG1, FG2, FG3, and FG4 in the drain regions. The contacts X1, X2, X3, and X4 connect between drain regions and metal. The source S and the drain D are indicated near the floating gate FG4.
FIG. 2 shows a cross section of the prior art device of FIG. 1 taken along line 2--2 in FIG. 1. The source region S and drain region D are shown as N+ doped regions in the P-sub 11. Above those elements is the tunneling oxide layer 12 having a thickness of about 100 .ANG.. The polysilicon floating gate FG3 is shown on tunneling oxide layer 12. The next layer is interpolysilicon ONO layer 16 upon which is formed the polysilicon 2 layer 20, which serves as the control gate.
FIG. 3 shows a cross section of the device 10 of FIG. 1 taken along line 3--3 in FIG. 1. The P-sub 11 is covered by the tunneling oxide layers 12 and 12' beneath the polysilicon 1 floating gate structures FG3 and FG4. Between the tunneling oxide layer sections 12 and 12' are located FOX regions 13.
Above the floating gate structures FG3 and FG4, is the interpolysilicon layer 16. Above the interpolysilicon layer 16 is a polysilicon 2 control gate layer 20'.